1. Field of the Invention
The present invention relates to integrated circuit packaging. In particular, the invention relates to a package with a reticulated bond shelf into which supporting components are mounted to provide high speed and high output drive interface circuits.
2. Description of Related Art
Known integrated circuits are mounted in packages as depicted in FIGS. 5 and 6. As depicted in FIG. 5, the package includes case C (typically of a ceramic material) with bonding wire shelf BWS integrally formed therewith. The package further includes wires W of a wire frame (see both FIGS. 5 and 6) integrally formed with case C. Ends E of wires W of the wire frame penetrate case C and are disposed on bonding wire shelf BWS. Semiconductor circuit S is mounted in case C and includes a plurality of bonding pads P. Then, fine wires G, typically gold, are connected between each pad P and corresponding ends E of wires W. Lid L (FIG. 5) is then sealed on case C, and excess perimeter metal is trimmed off of the wire frame (FIG. 6).
In FIG. 4, an output arrangement is depicted for high density MOS (metaloxide-semiconductor) circuits or CCD (charge coupled device) circuits. In high density circuits, semiconductor circuit S is mounted in case C and includes sense node N connected to the gate of an MOS transistor. The MOS transistor is arranged in a source follower circuit without a load resistor connected to the source terminal of the MOS transistor. Instead, the source of the MOS transistor is wired to bonding pad P. During package assembly, bonding pad P is connected through gold bonding wire G to end E of wire W. The assembled package is mounted on, and wire W is soldered into, a known type of printed wiring board (e.g., copper clad epoxy laminates). Similarly, resistor R and bipolar transistor Q are mounted on the printed wiring board. The printed wiring board connects the base of bipolar transistor Q with wire W and one end of resistor R. The other end of resistor R is connected to ground so that resistor R functions as a load for the source follower arrangement of the MOS transistor. Bipolar transistor Q is arranged as an emitter follower circuit.
High density circuits have very little drive capability. For example, the voltage at node N (FIG. 4) cannot drive a load resistor directly. Thus, the MOS transistor of semiconductor circuit S is arranged as a source follower to achieve a significant current source capability at bonding pad P. This current source capability is loaded by resistor R and is followed by an emitter follower. In known arrangement such as the circuit depicted in FIG. 4, the current source capability of the source follower circuit must not only drive the load caused by resistor R, it must also drive parasitic capacitance. The parasitic capacitance between wire W, the base of bipolar transistor Q and resistor R is typically 10 to 15 picofarads. This capacitance is one of the principal factors responsible for limitations in the speed performance of the circuit.